PCB Basics for Software Folks: From Schematic to Board

1) Start with a “first-board spec” (10 minutes)

Treat it like a README: constraints first, creativity second.

• 2-layer FR4, 1.6 mm, 1 oz copper (default friendly)
• No BGA, no 0.4 mm pitch parts, no RF antennas on v1
• Target fabrication rules: 6/6 mil trace/space and 0.3 mm drill (common)
• Define connectors, mounting holes, and power input early

2) Draw the schematic like code, then lint it

Your schematic is the source of truth. The PCB is the “compiled artifact”.

• Name nets (3V3, VIN, SDA/SCL) so debugging is sane
• Add decoupling caps next to each IC power pin (don’t “remember later”)
• Run ERC (Electrical Rules Check) and fix everything you understand
• Mark anything uncertain as “needs review” and resolve before layout

3) Place parts for current flow, not aesthetics

Think “data locality” but for electrons: short loops, clean return paths.

• Power path: input → regulator → bulk cap → loads (short and wide)
• Decoupling caps within a few mm of the IC pins
• Keep high-speed/clock traces short and away from noisy power switching
• Put programming/debug header somewhere you can actually reach

4) Before ordering, do the “3 export checks”

Most first-board failures are preventable with these final checks.

• DRC clean: no clearance/width errors
• Silkscreen readable: pin 1 markers, polarity, labels not on pads
• Manufacturing preview: inspect Gerbers + drill file like a final render

Schematic

The logical circuit: symbols connected by nets. This is where you express intent and correctness.

• Defines electrical connectivity
• Drives net names and BOM meaning
• Checked with ERC (electrical rules)

PCB layout

The physical implementation: footprints, copper traces, planes, holes, and mechanical constraints.

• Defines geometry (where parts and copper go)
• Drives manufacturability and signal quality
• Checked with DRC (design rules)

Trace

A copper “wire” on a layer. Width and length matter for resistance, heat, and signal integrity.

• Wider for power/high current
• Shorter for clocks/high-speed signals
• Controlled width/spacing for some differential pairs

Plane / pour

A large copper area (often ground) that provides low-impedance return paths and shields noise.

• Usually keep ground as a solid reference
• Split planes carefully (splits can create noisy return paths)
• Use stitching vias to connect ground regions

Functional constraints

• Power input range (USB? battery? VIN?) and max current
• Microcontroller/module choice and required peripherals
• Connectors (pin count, orientation, keyed vs not)
• Programming/debug access (UART/JTAG/SWD) and test points

Physical constraints

• Board size, mounting holes, enclosure clearance
• Keepouts (antennas, high-voltage, mechanical parts)
• LED/viewable elements and label readability
• Fabrication capability (trace/space, drill, layer count)

Verify these against the datasheet

• Pin numbering and orientation (pin 1 marker)
• Pad size and pitch (especially connectors and QFN/QFP)
• Courtyard/keepout (can parts physically fit side-by-side?)
• Thermal pad rules (if the package has an exposed pad)

Assembly-friendly defaults

• Prefer 0603/0805 passives for manual soldering
• Use well-known connector footprints (JST, pin headers) where possible
• Add clear polarity marks for diodes, electrolytics, LEDs
• Put reference designators where you can read them after assembly

Power placement rules

• Bulk cap near power entry (absorbs transients)
• Regulator close to input and load (reduce loop area)
• Short, wide traces for high-current paths
• Keep switching node copper small (if using switching regulators)

Signal placement rules

• Crystal/oscillator close to MCU pins (short traces)
• Keep sensitive analog away from switching power
• Route buses as a group (I2C/SPI) and avoid long detours
• Place connectors where cables won’t stress components

High-signal DRC issues

• Unconnected nets (ratsnest leftovers)
• Clearance violations (manufacturing failures)
• Too-thin power traces (voltage drop, heating)
• Silkscreen on pads (assembly problems)

High-signal ERC issues

• Power pins not powered (missing net labels)
• Inputs floating (missing pull-ups/pull-downs)
• Pin type conflicts (output↔output shorts)
• Unconnected pins that should be tied off per datasheet

Bring-up checklist

• Measure each rail (3V3, 5V, etc.) at a labeled test point
• Confirm reset line behavior and boot mode pins
• Verify programming/debug works before soldering “everything”
• Test one peripheral at a time (I2C scan, SPI ID, UART loopback)

BOM sanity = fewer surprises

A lot of “board doesn’t work” is actually “wrong part” or “wrong footprint variant.” Even a tiny script can catch missing fields or mismatched packages before you order.

import csv
import sys

REQUIRED = {"Reference", "Value", "Footprint", "Manufacturer Part Number"}

def load(path: str):
    with open(path, newline="", encoding="utf-8") as f:
        return list(csv.DictReader(f))

def main(path: str) -> int:
    rows = load(path)
    if not rows:
        print("BOM is empty.")
        return 2

    missing_cols = REQUIRED - set(rows[0].keys())
    if missing_cols:
        print("Missing BOM columns:", ", ".join(sorted(missing_cols)))
        return 2

    bad = 0
    for r in rows:
        mpn = (r.get("Manufacturer Part Number") or "").strip()
        fp  = (r.get("Footprint") or "").strip()

        if not mpn:
            bad += 1
            print(f"[NO MPN] {r.get('Reference','?')} {r.get('Value','?')} ({fp})")

        # Basic heuristic: warn on tiny passives for first boards
        if "0402" in fp:
            print(f"[WARN] 0402 part: {r.get('Reference','?')} ({r.get('Value','?')})")

    print(f"Checked {len(rows)} BOM lines. Issues: {bad}")
    return 1 if bad else 0

if __name__ == "__main__":
    sys.exit(main(sys.argv[1] if len(sys.argv) > 1 else "bom.csv"))

Mistake 1 — Trusting an unverified footprint

Everything looks right until the part physically doesn’t fit or pins don’t match pads.

• Fix: check pad pitch, pin numbering, and orientation against the datasheet.
• Fix: print the footprint at 1:1 on paper and place the part on it (surprisingly effective).

Mistake 2 — Missing decoupling (or placing it far away)

The MCU “sort of works” until Wi-Fi turns on, a motor switches, or an ADC looks noisy.

• Fix: put 0.1 µF caps near each IC power pin (short traces, short ground return).
• Fix: add bulk capacitance per rail near the loads and near the regulator.

Mistake 3 — Skinny power traces

Voltage drop and heat show up as “random resets” or flaky peripherals.

• Fix: widen power traces, especially to regulators, motors, LEDs, and radios.
• Fix: keep high-current loops short and avoid routing them through sensitive ground regions.

Mistake 4 — No debug access

The board is assembled… and now you can’t flash firmware or see logs.

• Fix: add a programming header (SWD/JTAG/UART) and label it on silkscreen.
• Fix: add test points for power rails, reset, and one bus line.

Mistake 5 — Silkscreen and polarity confusion

A reversed diode/LED or a rotated IC can waste hours.

• Fix: clear pin 1 markers, diode arrows, capacitor polarity, connector pin 1.
• Fix: keep reference designators visible after assembly (not under parts).

Mistake 6 — Ground plane chopped into islands

Noise problems appear because return current takes long detours.

• Fix: keep ground as continuous as possible, avoid unnecessary splits.
• Fix: add stitching vias and avoid routing that slices the plane under sensitive signals.

Schematic (logical) checklist

• All power rails named and consistent (VIN, 5V, 3V3)
• Decoupling caps present for every IC
• Reset/boot strapping matches datasheet (pull-ups/pull-downs)
• Connectors labeled (pin 1, polarity, purpose)
• ERC run and reviewed (no “mystery warnings”)

Layout (physical) checklist

• Board outline correct + mounting holes included
• Power traces wide + short; ground pour present
• Decoupling caps placed close to pins
• Silkscreen readable; polarity/pin 1 markers clear
• DRC clean (or each exception understood and justified)